This invention relates to a video display unit including a set top box for receiving digital broadcasting signals which multiplex digital data such as compressed video signals or program information and for decoding and outputting the selected video signals. This invention also relates to a program recording medium.
In accordance with the recent development of the digital technology, digital broadcasting services have been realized which use videos, audio, and data signals for broadcasting as digital signals in a unified way, and broadcast them by utilizing a satellite or the like.
In those services to provide tens or hundreds of channels of broadcasting by means of a compression multiplex technology represented by MPEG2 (standardized with ISO/IEC-13818) or the like. Each broadcasting service provider intends to complete a variety of services for implementing high definition video broadcasting and for realizing the differentiation such as an information service using still picture or the like by utilizing the characteristics of the digital broadcasting where all the signals for videos, audio, and data or the like are handled as digital signals, and a video display unit is required to cope with those.
An example of a conventional MPEG video decoder system is shown in FIG. 14, which will be described in operation in the following.
In FIG. 14, the numeral 100 denotes a system control means for controlling the entire system, the numeral 101 denotes a video decoding means for decoding MPEG, the numeral 102 denotes a frame memory for storing display data, and the video decoding means 101 stores video data to be decoded and graphics data of on-screen display (hereinafter referred to as OSD). The numeral 103 denotes a display timing generation means for generating a synchronizing signal or the like, the numeral 104 is a memory control means for controlling reading or writing of the frame memory 102. The numeral 105 denotes an output buffer means for temporarily storing the display data read by the memory control means 104. The numeral 800 denotes a video processing unit for generating display data by using the data of the output buffer means 105, and the numeral 801 denotes a control timing generation means for controlling the video processing unit 800.
FIG. 15 illustrates an exemplary internal configuration of the video processing unit 800 in the above mentioned MPEG video decoder system. The numerals 8001 and 8002 denote horizontal filter circuits for horizontal up/down scaling operations of the video data, the numeral 8003 denotes a vertical filter circuit for up/down scaling in the vertical direction the sequential two line data from the horizontal filters 8001 and 8002, and the numeral 8004 denotes a blending circuit for switching between video data from the vertical filter circuit 8003 and the OSD data.
FIG. 16(a) shows a video output format to be implemented at a receiver for digital broadcasting established by the DVB (Digital Video Broadcasting DOCUMENT A001-revision 1) standard.
In order to implement the horizontal and vertical up-scaling processing shown in FIG. 16(a), the horizontal filter circuit 8001 and 8002 as well as the vertical filter circuit 8003 are provided with circuits in advance corresponding to the following magnifications.
horizontal filter circuits: 3/4, 1, 9/8, 4/3, 3/2, 2, 8/3
vertical filter circuits: 1, 2
FIG. 16(b) shows a pan-scanning process, which cuts out and expands horizontally the central display portion (Pan and Scan Window) in case an input video with an aspect ratio 16:9 is outputted on a monitor with 4:3.
In this way, in a video display unit for a digital broadcasting receiver, the horizontal and vertical up-scaling processing of the video signals has become an indispensable function.
The MPEG decoder system in FIG. 14 is described in operation in the following.
The system control means 100 inputs a bit stream corresponding to a channel the user has selected into the video decoding means 101.
The video decoding means 101 picks out information for the input resolution of FIG. 16(a) in the bit stream to be transferred to the system control means 100. The video decoding means 101 performs the MPEG video decode processing by using the frame memory 102 as a reference frame buffer and a display frame buffer. A description for the MPEG decode processing is omitted in the detailed operation, since it doesn""t directly relates to the purpose of the present invention.
The system control means 100 draws the on-screen display (OSD) data for the frame memory 102 in parallel with the decode control. This is program table data called operational information of the menu or the like or the EPG (Electronic Program Guide). In the video display, the system control means 100 controls the memory control means 104 to read out the video data decoded from the frame memory 102 and the OSD data per line unit. The data read out per line unit is temporarily stored in the output buffer means 105.
The system control means 100, in compliance with the resolution information of the input video picked out of the video decoding means 101 and the aspect ratio of the output monitor indicated in advance by the user, sets the up-scaled ratio of the horizontal filter circuits 8001 and 8002 as well as the vertical filter circuit 8003 in the video processing unit 800 so as to control the up-scaling processing shown in the FIG. 16(a). The decode video processed for up-scaling is outputted externally after blended with the OSD data at the blending circuit 8004.
In this way, the conventional video processing unit in the MPEG decoder system is provided with a dedicated circuit corresponding to the up-scaled ratio set in advance and a blending circuit with the OSD data, to generate a display output complying to the resolution information or the like of the decode video.
FIG. 17 shows a block diagram of the MPEG decoder system for implementing a still picture display in addition to an video and an OSD displays in order to correspond to a still picture information service. The video processing unit 800 is provided with two system horizontal filter circuits 8001 and 8002 as well as a vertical filter circuit 8003 to control for video data and still picture data respectively and is further provided with a blending circuit (1) 8005 for switching between the video data and the still picture data.
In operation, the system control means 100 draws not only the OSD data but also the still picture data for the frame memory 102. The still picture data are sent by utilizing data broadcasting such as digital satellite broadcasting, or are sent through the telephone line. In any case, the data are obtained by the operation of the user and displayed by the control of the system control means 100. The still picture data written in the frame memory 102 are read out to the output buffer means 105 per line unit together with the video data and the OSD data by the memory control means 104. At this time, in case the vertical filter processing is performed for the video data, sequential two lines of data are read out for the video data.
Using those data, down-scaling processing is carried out independently for the video and the still picture data by the video processing unit 800 shown in FIG. 17, and by blending the result of this operation with the OSD data, an output video as shown in FIG. 17 can be gained.
As described above, the conventional video display unit is implemented by having a dedicated circuit as shown in FIGS. 15 and 17 corresponding to a different display specification depending on each service provider. Those are usually built in as part of the MPEG video decoder LSI circuit.
On the other hand, the digital broadcasting standards for the ground wave in the U.S.A. correspond to as much as high definition system with three kinds of numbers of scanning lines 1080, 720 and 480 and with two kinds of scanning systems, the progressive scanning and the interlaced scanning, which makes it possible to have broadcasting with 18 types of video formats by combining those. To output those on a TV monitor, a scaling processing other than that shown in FIG. 16(a) is necessary. And an EPG display or the like by the above mentioned still picture service or the down-scaling video are expected to be required to cope with more filter operations as a video display unit.
In this way, a conventional video display unit, however, requires a different dedicated circuit depending on a service provider, and in order to correspond to a plurality of broadcasting services, there are problems such that the total circuit is increased because of the necessity of different circuits to have the individual display requirements, or the development cost is increased for the need of developing different types of LSI for the optimization depending on the services.
There also is a problem with expanding the system because there is no other method than building in a necessary circuit in advance in order to deal with processing required in future.
Taking those problems with the conventional video display unit into consideration, it is a purpose of the present invention to provide a video display unit to be able to limit the increase of development cost compared to the prior art.
Taking those problems with a conventional video display unit into consideration, it is also a purpose of the present invention to provide a video display unit to be able to limit the increase of the development cost compared to a prior art, and to have a better flexibility for the future expansion of the system.
A 1st invention of the present invention is a video display unit characterized by comprising:
a frame memory storing display data;
a display timing generation means for generating a display timing;
a memory control means for reading out display data from said frame memory by synchronizing to said display timing generation means;
an output buffer means for temporarily storing display data read out by said memory control means;
an arithmetic unit for generating display data by carrying out at least one operation within one period of pixel clock;
a data selection means for reading out display data from said output buffer means by synchronizing to the pixel clock and for selecting data inputted to said arithmetic unit; and
an instruction sequencer for controlling said data selection means and said arithmetic unit by synchronizing to the timing of said display timing generation means.
A 2nd invention of the present invention is a video display unit according to said 1st invention characterized by said instruction sequencer having:
an instruction memory for storing control information to control said arithmetic unit and said data selection means;
an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock; and
an instruction decoder means for decoding said read out instructions and for controlling data inputted to said arithmetic unit by said data selection means.
In this way, a video display unit according to the present invention, for example, is provided with an arithmetic unit which performs an arithmetic processing at least once within a period of a pixel clock and an instruction sequencer for controlling the selection and the output of data to be inputted to this, and by synchronizing this instruction to the display clock for execution, implements video up/down scaling processes as well as a blending process with the OSD.
This configuration allows the arithmetic unit and the instruction sequencer to be in a common circuit for corresponding to a plurality of display specifications by switching instructions instead of an implementation method of providing a dedicated circuit for each required specification according to a conventional unit.
This also allows the instructions stored in the instruction sequencer to be re-writable so as to be able to correspond more display specifications easily.
A 3rd invention of the present invention is a video display unit according to said 2nd invention characterized by:
said instruction memory storing execution instruction within at least one period of the pixel clock; and
said instruction execution means reading out repetitively said instruction memory by synchronizing to the pixel clock.
This can implement video display processes such as the video up/down scaling as well as a synthetic process with the OSD with only a little instruction memory just for one pixel.
A 4th invention of the present invention is a video display unit according to said 2nd or 3rd invention characterized by having an operational result buffer means for enabling to temporarily memorize outputs of said arithmetic unit and for enabling to output to said data selection means.
This allows to select the arithmetic operational result as an arithmetic unit input freely even on and after the next cycles by storing temporarily the arithmetic operational results so that more kinds of arithmetic processes can be controlled by instructions.
A 5th invention of the present invention is a video display unit according to either one of said 2nd to 4th inventions characterized by having a write back means for writing back data outputs from said arithmetic unit to said output buffer means and the instruction sequencer controlling said write back means.
This allows to provide a screen arranging and displaying a plurality of reduced videos by the function writing a decode video after up-scaling or down-scaling back to the frame memory.
A 6th invention of the present invention is a video display unit according to either one of said 2nd to 5th inventions characterized by said instruction sequencer being provided with a switching means for the number of instructions read out within one period of pixel clock.
This allows to implement a video process only by changing the number of executable instructions even in case 480 or 1080 lines of interlace-scanning and 480 or 720 lines of progressive scanning are mixed for broadcasting, by switching the number of executable instructions within one period of the pixel clock in accordance with the decode video.
A 7th invention of the present invention is a video display unit characterized by comprising: a memory frame for storing display data; a display timing generation means for generating a display timing; a memory control means for reading out display data from said frame memory by synchronizing to the generated display timing; an output buffer means for temporarily storing display data read out by the memory control means; a display data read out means for controlling reading out of display data from said output buffer means in accordance with a desired display specification; a plurality of video processing units for processing display data read out from said display data reading out means; an output selection means for selecting output data of said plurality of video processing units; and an instruction sequencer for controlling said plurality of video processing units and said output selection means by utilizing processing instructions corresponding to a desired display specification within processing instructions corresponding to a plurality of display specifications stored in advance.
A 8th invention of the present invention is a video display unit according to said 7th invention characterized by: each of said video processing units comprising an arithmetic unit for carrying out at least one operation within one period of the pixel clock and for generating display data, and a data selection means for reading out display data by synchronizing to the pixel clock from said output buffer means and for selecting data to be inputted to said arithmetic unit; and said instruction sequencer comprising an instruction memory storing control information for controlling said arithmetic unit and said data selection means, an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock, and an instruction decoder means for controlling data inputted to an arithmetic unit within said plurality of video processing unit by decoding the read out instructions.
The above mentioned configuration allows the arithmetic unit and the instruction sequencer to be in a common circuit in order to be able to correspond to a plurality of display specifications by switching instructions instead of applying an implementation method for providing the dedicated circuit for each required specification such as that in a conventional unit.
In this way, by providing an arithmetic unit for carrying out an arithmetic process at least once within a period of the pixel clock and the instruction sequencer for controlling the selection and the output of the data to be inputted to this, and by synchronizing this instruction to the display clock so as to execute this instruction, video up/down scaling processes and a blending process with the OSD are implemented. Accordingly, a video display process such as video up/down scaling as well as a blending process with the OSD can be described with instructions of the instruction sequencer. And because of the configuration where the same video processing units are arranged in parallel and one instruction sequencer controls this, the pixel clock and the up-scaling in accordance with the arithmetic processing contents have become easy with a simple configuration.
A 9th invention of the present invention is a video display unit according to said 7th invention characterized by: each of said video processing units comprising an arithmetic unit for carrying out at least one operation within one period of the pixel clock and for generating display data, and a data selection means for reading out display data from said output buffer means by synchronizing to the pixel clock and for selecting data to be inputted to said arithmetic unit; and said instruction sequencer comprising an instruction memory storing control information for controlling said arithmetic unit and said data selection means, an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock, and an instruction decoder means provided in each of said plurality of video processing units and for controlling data inputted to an arithmetic unit within the video processing unit by decoding said read out instructions.
This configuration makes it possible to describe a video display process such as video up/down scaling operations as well as a blending process with OSD with instructions of the instruction sequencer. And because of the configuration where the same video processing units are arranged in parallel, which are controlled by the instruction decoder corresponding to each of the video processing units, it has become easy to expand in accordance with the pixel clock and the contents of arithmetic process with a simple configuration.
A 10th invention of the present invention is a video display unit according to said 8th or 9th invention characterized by said instruction memory storing an execution instructions within at least one period of pixel clock, and said instruction execution control means reading out said instruction memory repetitively by synchronizing to the pixel clock.
This allows to implement with only a little instruction memory just for one pixel.
A 11th invention of the present invention is a video display unit according to either one of said 8th to 10th inventions characterized by each of said video processing units having an operational result buffer means for enabling to temporarily memorize outputs of said arithmetic unit and for enabling to output to said data selection means.
In this way, by storing temporarily the arithmetic operational result, it has become possible to select the arithmetic operational result as an arithmetic unit input freely on and after the next cycle so that more kinds of arithmetic processing can be controlled by the instructions.
A 12th invention of the present invention is a video display unit according to either one of said 8th to 11th inventions characterized by having a write back means for writing back output data from each of said video processing units to said output buffer means and said instruction sequencer controlling said write back means.
In this way, a screen which arranges and displays a plurality of reduced videos can be provided by the function of writing decode videos after up/down scaling into the frame memory.